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authorVG <vg@devys.org>2015-01-28 00:03:35 +0100
committerVG <vg@devys.org>2015-01-28 00:03:35 +0100
commitcbb3c9832bbe31d741930d43d3e21a04abeb12f8 (patch)
tree1338bc0b6786a745d5d920b1aa6b2c0d1e645e5c /main.c
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first commit
Diffstat (limited to 'main.c')
-rw-r--r--main.c65
1 files changed, 65 insertions, 0 deletions
diff --git a/main.c b/main.c
new file mode 100644
index 0000000..cd3cf6e
--- /dev/null
+++ b/main.c
@@ -0,0 +1,65 @@
+#include <avr/io.h>
+#include <avr/interrupt.h>
+#include <util/delay.h>
+#include "uart.h"
+
+#define SET_PWM(a) (OCR0A = (a))
+
+void setup(void);
+
+int main(void)
+{
+ uint8_t output = 0, c;
+
+ setup();
+
+ for (;;) {
+ switch((c = uart_getchar())) {
+ case '?': break;
+ case 'n':
+ case '0': output = 0; break;
+ case 'y':
+ case '1': output = 1; break;
+ case 't':
+ case 'T': output ^= 1; break;
+ }
+
+ uart_putchar(c);
+
+ if (output)
+ SET_PWM(40);
+ else
+ SET_PWM(1);
+
+ _delay_ms(1000);
+ SET_PWM(0);
+ }
+
+ return 0;
+}
+
+void setup(void)
+{
+ /* serial */
+ uart_init();
+
+ /* Initialize timer for PWM
+ *** PWM with timer1 management:
+ * TCCR1A-COM1A1:
+ * TCCR1A-WGM10:
+ * TOP = 0x00FF
+ * frequency is : 12 MHz(fclk) / 256(prscl) / 255 (top)/ 2 = 91.91Hz
+ * frequency is : 18.432 MHz(fclk) / 256(prscl) / 255 (top)/ 2 = 141.18Hz
+ * frequency is : 18.432 MHz(fclk) / 1024(prscl) / 255 (top)/ 2 = 35.29Hz
+ * frequency is : 16 MHz(fclk) / 1024(prscl) / 255 (top)/ 2 = 30.64Hz
+ * TCCR1B CS12 = 256 prescaler, CS12 + CS10 = 1024 prescaler
+ *
+ * 23/24 =~ 1.5ms
+ */
+ TCCR0A |= _BV(COM1A1) | _BV(WGM10);
+ TCCR0B |= _BV(CS12) | _BV(CS10);
+ /* TIMSK0 |= _BV(TOIE0); */
+
+ /* pwm output; */
+ DDRD |= 0xFF;
+}